“These new technologies can help in addressing the demands of high-performance computing applications which require high memory bandwidth and low power consumption with reduced power supply noise,” according to the Institute.
BBCube stacks a processor on top of a stack of extra-thin DRAM die using a combination of wafer-on-wafer (WOW) and chip-on-wafer (COW) techniques.
Having the processor on top aids heat extraction, and the Institute’s face-down COW process was initially developed to get away from soldered interconnects and instead uses ink-jet selective adhesive deposition at room-temperature.
Used on 300mm wafers, it has achieved 10μm chip-to-chip spacing and <10ms mounting time.
“More than 30,000 chips of various sizes were fabricated onto the waffle wafer without any chip-detachment failures,” said project researcher Norio Chujo.
The first ECTC BBCube improvement paper covered a custom adhesive, dubbed DPAS300, optimised for thermal stability in COW stacks of extra-thin wafers.
“By carefully designing the chemical properties, [the] novel adhesive material can be used in both COW and WOW processes,” said the Institute. “Composed of an organic-inorganic hybrid structure, it] exhibited appreciable adhesiveness and heat resistance during experimental studies.”
The second paper described improved power distribution, with embedded decoupling capacitors added between the DRAM stack and the top processor, redistribution layers implemented on the waffle wafer, and through-silicon vias in wafer lanes and DRAM scribe lines (see diagram).
This “reduced the energy required for data transmission to one-fifth to one-twentieth of that in conventional systems, while also suppressing power supply noise to below 50mV,” claimed Chujo.
If you have access to ECTC papers, more details are available:
‘Face-down bonding and heterogeneous chiplet integration by using bumpless chip-on-wafer (COW) with waffle wafer technology’
‘Advanced resin material enabling room-temperature bonding for WOW and COW 3DI applications’
‘BBCube 3D: Fully vertical heterogeneous integration of DRAMs and xPUs using a new power distribution highway’
