At yesterday’s Altera Innovators Day event (formely known as Intel FPGA Technology Day), Altera, newly launched as an independent subsidiary of Intel, announced the release of the Agilex 3 line of FPGAs.
Altera’s new Agilex 3 FPGA line. Image used courtesy of Intel
Altera launched the new FPGAs alongside the latest update to its Quartus Prime Design Software FPGA software suite and 11 new Agilex 5 FPGA development kits and system-on-module (SoM) boards. The Agilex 3 targets mid-range applications where performance is important, but cost and power consumption are of greater priority. The Quartus FPGA and system-on-chip (SoC) toolchain supports the latest devices and improves useability and compile times.
All About Circuits learned more details about the new series from Altera’s CEO Sandra Rivera.
Agilex 3 FPGA Line
The Agilex 3 series has an on-chip dual-core Arm Cortex A55 hard processor and AI capabilities infused into the FPGA fabric. The combination of AI functionality and hard processor cores enables real-time processing in time-critical applications like automotive and Internet of Things (IoT) devices. The Agilex 3 line also comes with security-specific enhancements over the prior generation Cyclone V chips, such as bitstream encryption, authentication, and physical anti-tamper detection.
“This series is for applications that are in industrial manufacturing, surveillance, medical, test and measurement, and edge computing, where you need, frankly, a lot of compute, but you don’t have the flexibility and headroom on power footprint that you would in a big data center,” Rivera said.
Some key features of the new FPGA series include:
- 25K–135K logic elements
- 1.9X FPGA fabric performance with Hyperflex architecture
- DSP and Tensor blocks within FPGA fabric
- PCIe 3.0
- LPDDR4
- 12.5 Gbps transceivers
- 38% lower power consumption vs. competing FPGAs
Vision processing, image recognition, and factory automation are in high demand. Offering FPGAs that fit the functionality, cost, and power requirements of these applications increases maintainability and accelerates time to market.
FPGA Hyperflex Architecture
Altera’s Hyperflex architecture, added to the Agilex 3 chips, delivers nearly double the performance over the prior generation. Altera refers to Hyperflex as a “register everywhere” architecture. It enables more efficient routing by packing bypassable hyper-registers into the device core. Signals can be routed either through the register or bypass the register and go straight to the multiplexor. This capability can reduce propagation steps and increase bandwidth and clock speeds.
When combined with multiple high-speed transceivers, the new series operates up to 12.5 Gbps and supports LPDDR4 memory. Altera says the Hyperflex-equipped Agilex 3 delivers 1.9x higher performance than the Cyclone V.
Design Suite Optimized for Time to Market
Altera optimized the Quartus Prime Software version 24.3 design suite for ease of use and solid performance. The updates to Quartus give the new FPGA line a full-stack solution, including FPGA development and software for soft and hard processor cores.
“The [Quartus Prime tool chain] is designed to help [developers] get to their applications and use cases running quickly and efficiently so they can get to market faster,” Rivera said.
The software exhibits 29% faster compile times, supports more FPGAs, and comes with new OS and RTOS support for the Agilex 5 hard processors subsystem. The series’ faster compile times and greater integrated functionality significantly improve efficiency.
“We’ve got almost 30% faster compile times, which means that the developer can get maybe an extra turn of an algorithm, an application, or a design that they’re trying to test out, and that just makes their development time more efficient,” Rivera said. “If you can get from a three-hour compile time down to a two-hour compile time, then you get more software runs per day, and accelerate your time to market.”
The 3 Series’ Place in the Agilex Family
The Agilex 3 line complements the rest of the Agilex line as a cost and power-optimized FPGA. While Agilex 7 and 9 are the top performers and Agilex 5 focuses on performance with adaptations for lower power consumption, the 3 series delivers solutions that meet low-cost and low-power requirements. Agilex 3 also brings AI functionality to the cost-optimized end of Altera’s FPGA line with tensor computing blocks and AI-optimized DSP sections.
Altera Agilex 3 series compared to other Agilex FPGAs. Image used courtesy of Altera
In-FPGA AI capabilities enable edge AI processing without an additional discrete GPU or tensor processor. Efficient edge AI requires capabilities not typically found in conventional processors or FPGAs. The Agilex 3 adds tensor processing and DSP functionality to the field-programmable fabric. This provides GPU-like capabilities at a level commensurate with the edge AI requirements.
The Agilex 3 FPGAs are scheduled for availability in Q1 2025. The new Agilex 5 development kits are available from a number of partners and are showcased on Altera’s Partner Showcase site.
