Today, every semiconductor foundry provides an extensive range of libraries for its processes. There is also a huge variety of third-party intellectual property (IP) blocks available. As the foundry and third-party IP continue to grow, who needs customization? Quite possibly, you!
In this article, we will discuss why the ability to create custom fundamental IP—custom cells and libraries—should be a factor in selecting the design services provider for your next design.
The PPA Vs. Cost Challenge
Often, SoC designs push up against the performance, power, and area (PPA) boundaries achievable by an affordable process node. The required PPA may be just outside the envelope. In these cases, you typically have only three choices:
- Move the design to a more advanced, complex, and expensive process node.
- Back off on the design requirements.
- Forge ahead with the design and risk missing the design requirements.
We want to consider a fourth alternative: working with a design-services partner that can develop custom cells that take maximum advantage of the foundry process capabilities. This can allow you to meet your design needs while using an affordable process.
However, creating custom IP requires special skills in physical design. It also requires the IP creators to have an intimate relationship with the foundry. Changing the number of routing tracks in a cell library, reallocating or changing the number of metal layers, resizing transistors, and relocating contacts all require an accurate, step-by-step understanding of the target process and a great relationship with the process engineers.
An AI Project Example
An example might illustrate the value of custom IP and show how its use fits into the design flow.
Faraday Technology recently engaged with a customer who was designing a chip for artificial intelligence (AI) applications. As in most AI scenarios, computing performance was the most crucial design requirement. However, in this application, power consumption and cost were also critical.
The combination of requirements led the customer to select a relatively mature process node rather than the most advanced one. Soon, the focus of the design effort was on getting a floorplan for the customer’s innovative architecture that could achieve the die-size and performance goals.
This pursuit quickly came down to configuring critical SRAM arrays. After experimenting, the customer concluded that the existing SRAM IP options would not work—they needed a custom SRAM block. So, they entered discussions with Faraday on creating a custom block.
SRAM Macro Redesign
Our response began with information gathering. A Faraday IP design team and the customer’s chip architects discussed the requirements for the custom SRAM in the context of the overall chip requirements. We also studied this customer’s previous chip project, working to understand their architectural thinking and design style.
After analysis we concluded that the custom SRAM the customer wanted was feasible in their chosen process. Figure 1 shows how the new custom SRAM macro allowed the creation of a new floorplan that reduced area by 5% with the required SRAM configuration, a common address path, and MBIST circuitry.
Figure 1. SRAM IP customization for area reduction
While the new SRAM macros and floorplan were helpful, we reached another important conclusion—this process node could not support the customer’s PPA point without additional design customization.
Standard Cell Library Customization
To achieve the customer’s goals in this target process, we would need to optimize the existing cell libraries. This would require changes to the metal routing resources (Figure 2).
Figure 2. Standard cell metal routing resources
We could reorganize the process’s metal layers to provide enough routing resources to achieve the desired floorplan in conjunction with the custom SRAM blocks. Figure 3 demonstrates how adding two single-pattern metals can increase the available routing resources.
Figure 3. Adding two single-pattern metal layers provided more standard cell routing resources
Process Corner Design and Simulation
Finally, we would need to design the chip to operate at a custom process, voltage, and temperature (PVT) corner using the highest voltage for which we could guarantee chip reliability.
All of these changes were non-trivial customizations. But together, they would put the chip on the needed PPA point in the chosen process.
Reaching Agreement
An essential truth about custom IP is that success requires collaboration. Once we had a proposal for these customizations, we presented them to the customer, along with our estimates of their impact on the design. We went through several iterations of presentation, comment, and revision to reach a detailed plan accepted by our team and the customer.
Once this agreement was in place, we proceeded to Phase 2 of our custom fundamental IP design flow, as illustrated in Figure 4.
Figure 4. Custom fundamental IP design flow
Silicon Validation
The next step was to validate the customizations in silicon. This would prove that the changes were compatible with the chosen manufacturing process and produced the customer’s desired results.
We first designed the custom SRAM block and new high-speed digital logic library. Then, we created test structures using the new IP, took the design through our physical design chain, taped out, and fabricated test chips.
The test silicon proved that the customizations worked. It also allowed us to characterize the new IP at the new target voltage. This data would make the next step possible.
Integrating Into the Design Flow
An important consideration for custom IP is how easy—or hard—it will be for the chip design team to use it. In this design, where the customer was using Faraday’s standard design flow, our goal was to make the custom IP completely transparent to the chip designers.
This meant integrating the design data for the customizations into the various files in the process design kit (PDK). In this way, floorplanning, synthesis, timing, place-and-route, and analysis tools would use the new IP without any special action by the chip designers.
As the customer began their design, Faraday’s custom IP team transitioned into another role, supporting the chip design team. As of this writing, the chip design effort is still progressing toward tapeout. No major issues with the custom IP have appeared. All of the techniques applied in this customization have been used previously, and the aggressive PVT corner is still within the range of guaranteed chip reliability, so we are confident.
Custom IP Provides a Vital Alternative
In this design, our customer sought a floorplan and performance level slightly beyond the capabilities of existing libraries for their chosen process. Rather than move to a more complex and expensive node, the customer chose to work with Faraday to create custom IP to meet their specific design needs. We will license the custom IP to them at the same rate as the standard Faraday-made IP without a surcharge for customization.
Together, the ability to use a more mature process node, with its lower design cost and unit cost, and the performance and area impact of the custom IP are expected to give the customer a competitive edge in the increasingly crowded AI chip market.
Custom IP cannot be a substitute for choosing an appropriate technology node for a challenging chip design. However, when a particular process’s standard IP offers a PPA point close to what is needed, and architectural exploration indicates that there are only a few specific barriers to meeting the design goals, custom IP can often be a bridge to success.
This short paper has necessarily lacked detail. If you wish more information about this specific design—to the extent that we can disclose it—or more about Faraday’s custom IP program, please reach out to us at faraday-tech.com.
Featured image used courtesy of Adobe. All other images used courtesy of Faraday Technology.
Industry Articles are a form of content that allows industry partners to share useful news, messages, and technology with All About Circuits readers in a way editorial content is not well suited to. All Industry Articles are subject to strict editorial guidelines with the intention of offering readers useful news, technical expertise, or stories. The viewpoints and opinions expressed in Industry Articles are those of the partner and not necessarily those of All About Circuits or its writers.
