In embedded systems, it is common to use discrete logic devices, such as the 74’HC series, in many applications. The advantage that these logic devices bring is that they operate independently of the microcontroller (MCU) and can respond much faster than software. However, these devices add to the Bill of Materials (BOM) and require additional PCB area.
To solve this problem, many Microchip microcontrollers incorporate a peripheral known as the Configurable Logic Cell (CLC) on PIC MCUs or a similar peripheral known as Configurable Custom Logic (CCL) on AVR MCUs. Both peripherals implement software-defined custom logic that can be executed independently of the CPU. In other words, once the custom logic function has been setup, its behavior is independent of the microcontroller.
These peripherals are helpful tools for developing simple logic circuits, mixing signals together, and integrating with other hardware peripherals. But one limitation of these peripherals is that the amount of logic per instance is very small. Each CLC is approximately equivalent to a single Look-Up Table (LUT), while the CCL is an instance with a couple of independent LUTs inside.
Introducing the Configurable Logic Block
A new type of logic peripheral, the Configurable Logic Block (CLB), was developed to support more complex applications, as shown in Figure 1. It was first introduced in the PIC16F13145 family of microcontrollers.
Figure 1. Block diagram of the configurable logic block.
Note that the CLB does not necessarily replace the CLC or CCL peripherals. Microcontrollers may have both CLC/CCL(s) and a CLB.
The CLB on the PIC16F13145 family is composed of four sets of Logic Groups, each containing eight Basic Logic Elements (BLEs). BLEs across logic groups are connected, with each logic group a representation of two GPIO outputs and an optional interrupt for the CPU.
Other elements in the CLB include:
- A dedicated 3-bit hardware timer with decoded outputs
- An edge detector for input signals
- A 32-bit output register for debugging
In addition, other Core Independent Peripheral outputs on the microcontroller can be used as inputs to the CLB for more complex designs.
The CLB l is initialized from the microcontroller’s memory and can control pins directly from the fabric itself via Peripheral Pin Select (PPS). PPS allows the user to reassign the I/O pins used with the hardware peripherals for greater design flexibility. For instance, if RA1 was used for the SPI Clock and RA6 would be more advantageous, then PPS could remap the pin.
All BLEs share a common clock across the fabric, the source of which is configured in software along with an optional clock divider. The CLB can use one of the internal clock sources from the microcontroller or an externally provided source. When operated at 5.5 V, the BLEs have a typical propagation time of less than 6 ns.
CLB Synthesis
Since the CLB is substantially more complex than the CLC or CCL, a new tool known as the CLB Synthesizer was developed. The CLB Synthesizer provides a graphical interface for configuring the logic, as shown in Figure 2.
Figure 2. CLB Synthesizer demonstrating a Phase-Shift Keying (PSK) example
In addition to logic primitives, the Synthesizer also supports libraries of higher-level logic blocks, which can be pre-provided or custom-built by the user.
When interacting with the graphical tool, a Verilog module is generated behind the scenes for synthesis. If the developer prefers to write their own Verilog or has a file ready, the file can be directly imported into the tool as a module.
The output of the CLB Synthesizer is an assembly file containing the bitstream to set up the CLB and some source code to configure the CLB as a peripheral. This tool can be run through MPLAB Code Configurator (MCC) or via a standalone online tool. The MCC is a code generation utility that allows users to set up and configure the peripherals in the microcontroller using a visual interface. After configuring the hardware peripherals, the MCC generates an initialization code and a device API.
At runtime, the CLB bitstream is loaded directly from program memory using on-board hardware. This implementation benefits the program by allowing for a change in the CLB configuration while the program is running. The loading process can be repeated with a different bitstream stored in device memory.
Design Examples using the CLB
To demonstrate applications of the CLB, we’ll discuss two examples:
- A 7-segment display converter
- An SPI to WS2812 serial data converter.
These use-case examples are building blocks that can be copied and used as part of a complete solution. They are intended to demonstrate the CLB’s utility in designs.
7-Segment Display Converter
7-segment displays can be driven from the normal set of I/O pins. A standard implementation usually requires a software-defined lookup table to convert the input number into the correct output pattern for the display.
In this implementation, the CLB acts as a hardware lookup table. The desired output character (0 to F) is loaded into the CLB input register from the software. Each output segment of the display is controlled by a LUT which maps the inputs to the outputs.
This use-case example was used internally to build a new control board for a timekeeping system. The original user interface was developed in the 1980s with 74’HC series logic. Using CLBs to upgrade the design, a single 20-pin microcontroller can implement the display and keypad logic.
As demonstrated in Figure 3, this significantly reduces the Bill of Materials (BOM). The original board at the top has many more components than the new design at the bottom, which uses an MCU with CLBs.
Figure 3. Comparison of the original 7-segment display PCB (top) with the new PCB using CLBs (bottom). (click to enlarge)
SPI to WS2812 Serial Data Converter
WS2812 is a 1-wire serial protocol for controlling arrays of LEDs with pulse-width modulation. In this case, the SPI hardware is used as a shift register for the data to be sent to the LEDs, while the CLB converts SCLK and SDO into the expected output.
This is implemented using a mono-triggered 3-bit counter, a D-latch with Enable, and a 4-input LUT, as shown in Figure 4.
Figure 4. Block diagram of the SPI to WS2812 serial data converter. (click to enlarge)
The trick to this implementation is the clock sources for the SPI and CLB. The SPI clock is set to idle HIGH, change state on the rising edge, and run at the 800 kHz frequency of the WS2812 output. The CLB’s 8 MHz clock source is 10x faster.
When SCLK is LOW, the 3-bit counter is triggered and begins to count. When the counter reaches 7 (0b111), it stops and remains at 0 until the next low period of the clock pulse.
The output of the counter is fed into a 4-input LUT along with a latched version of the output data. This sets the output pattern of the data, which is visible on the right side of Figure 4. After the counter resets, the counter output will remain at 0 to complete the cycle. Then, if needed, the next byte in the SPI hardware is transmitted, repeating the cycle.
Advantages of Configurable Logic Blocks
Both examples demonstrate the advantage of discrete logic inside a microcontroller. The hardware peripherals offload tasks from the CPU, which can improve response time and power usage while reducing part count. The CLB enables the development of complex applications that were previously impossible to implement inside of a microcontroller. Currently, the CLB can be found on the PIC16F13145 family of microcontrollers which are available directly from Microchip Direct or other electronics distributors.
Author’s note: The 7-segment display converter example was developed by Josh Booth, and the SPI to WS2812 converter example was developed by Petre Teodor-Emilian.
All images used courtesy of Microchip Technology.
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