E-Trace defines an approach to processor tracing that uses a branch trace, intended for debugging any size of application up to super computers.
The documentation specifies the signals between the RISC-V core and
the encoder (or ingress port), a compressed branch trace algorithm, and a packet format to encapsulate compressed branch trace information.
“These new specifications accelerate embedded and large-system design,” RISC-V CTO Mark Himelstein. “Debugging is one of the hardest things to do on a chip. E-Trace for RISC-V creates a standard way to do processor trace that’s extremely efficient and is especially useful in embedded system design.”
RISC-V specification for SBI creates architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode (S-mode or VS-mode).
“This abstraction enables common platform services across all RISC-V operating system implementations,” according to the organisation. “Many RISC-V members have already implemented the Risc-V SBI specification in their solutions, so ratifying the specification will ensure a standard approach across the entire ecosystem, ensuring compatibility.
In the pipeline are a UEFI (unified extensible firmware interface) specification and the RISC-V Zmmul multiply-only extension, both currently with the organisation’s technical steering committee – the latter is aimed at low-cost implementations that require multiplication but not division, and is part of the RISC-V Unprivileged Specification.
At Embedded World, RISC-V International is hosting a pavilion of member-company innovations, including contributions from Andes Technology, CAES – Cobham Gaisler, Canonical Ubuntu, Codasip, Codeplay, Digital Core Technologies, GreenWave Technologies, Imperas, OpenHW Group, SiFive, Syntacore and Ventana Micro.
The Electronics Weekly stand is at 4A-628. Come and say hello if you’re at the show.
