The workshop is all about making imec’s Pathfinding Process Design Kit (P-PDK) for advanced logic technologies accessible to industry and academia.

It provides participants with a collection of code and files, bringing them up to speed on the digital design of N2 technology.

One of the key concepts covered was system-technology co-optimization (STCO).

For years, the industry focused on design-technology co-optimization (DTCO) to keep advancing – but as nodes get smaller, achieving performance gains becomes more challenging.

So, what is needed today are strategies that consider the entire system. Think of backside power delivery network (BSPDN) approaches – to give just one example. These are the types of functionalities that are part of imec’s P-PDK library, allowing participants to assess – and experiment with – specific N2 design features.

The workshops span one and a half days. The first day consists of a seminar providing a comprehensive overview of imec’s P-PDK, while the second half-day focuses on hands-on training.

Participants learn how to install the PDK and use electronic design automation (EDA) tools from Synopsis and Cadence, working through digital flows and exercises to gain a practical understanding of how different design strategies affect size and performance.

“By hosting this training and exploring opportunities for follow-up sessions, imec pursues a threefold objective. First, we aim to disseminate N2 technology to the design community and involve people in concepts like STCO at an early stage. Second, imec seeks to train participants in the specifics of advanced nodes, including new features such as BSPDN. Finally, we hope to motivate academic institutions to accelerate electronics research by exposing their members to the latest technological challenges and potential solutions.” – Anita Farokhnejad, R&D team leader, PDK enablement (pictured) & Sara Louahdi, imec.

For more about imec’s upcoming P-PDK workshops: