Lattice Semiconductor, a longtime player in the low-power, low-cost FPGA industry, recently released the MachXO5D-NX family. The mid-level family combines low cost and low power with a broad range of peripherals and security features, making it useful for secure edge devices.
MachXO5 development board.
By their very nature, field programmable gate arrays (FPGAs) pose unique security challenges and opportunities. While field programmability can be a gateway for those with nefarious intent, it also gives manufacturers the opportunity to adapt and update security after deployment.
Lattice designed the MachXO5D-NX family of advanced secure-control FPGAs with a set of built-in hardware encryption and security features. This gives the family the security of fixed hardware and the flexibility of an FPGA. With on-chip Flash and hardware encryption, the FPGA line can be built with fewer chips, which prevents code capture at load time.
The Three-Chip MachXO5D-NX Family
The three-chip family comes with a range of logic cells:
- FMXO5-25: 27k logic cells
- LFMXO5-55T: 53k logic cells
- LFMXO5-100T: 96k logic cells
Other features of the family include 20 to 156 sysDSP 18×18 multipliers and 1.9 Mb to 7.3 Mb of embedded RAM in EBR or LRAM form. The family also ranges from 200 to 300 high-performance, wide-range, and multi-voltage I/O.
MachXO5-NX DSP block and register layout.
Multipliers and DSP cells enable edge AI or other math-intensive applications. They come with a wide set of built-in peripherals, including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, Gigabit Ethernet, and PCIe (Gen1 and Gen2). The chips have embedded Flash memory for on-chip, multi-boot, and user flash memory (UFM). In addition to the onboard distributed RAM, EBR, and LRAM memory blocks, the chips have built-in interfaces for DDR3, DDR3L, and LPDDR4 up to 1066 Mbps.
The chips are supported by the Lattice Radiant design suite and synthesis libraries from popular design tools. Lattice has an extensive library of pre-engineered soft core and standardized IP modules for use within the new FPGA family.
Root of Trust and Other Security Features
The root of trust (RoT) is a secure area on a chip that contains keys for cryptographic functions. The MachXO5D-NX family members come with a hard silicon cryptographic engine with advanced encryption standards (AES), hashing algorithms, and a true random number generator (TRNG). Each includes a unique secret identity (USID) to protect device identity for additional security.
The devices are crypto-agile, which means they can switch between multiple cryptographic algorithms or methodologies. The chips support Commercial National Security Algorithms (CNSA) specified for bitstream and user data protection. Standards supported include AES-256, ECDSA-384/521, SHA2-256,384/512, and RSA 3072/4096.
Adding encrypt and decrypt capability into an FPGA is a common design feature. However, by including protection in hard silicon, no FPGA fabric has to be dedicated to the security features that nearly all applications should have.
MachXO5-NX DSP cryptographic engine block diagram.
The Lattice Nexus platform is built on a low-power 28-nm fully-depleted, silicon-on-insulator (FD-SOI) process. FD-SOI features reduced leakage current by placing an ultra-thin layer of silicon over a buried insulator. The layered architecture reduces substrate bulk and negates the need to dope the channel, creating fully depleted transistors. This process allows the Lattice parts to operate with 75% lower power and a 100x drop in soft errors. A low soft error rate equates to a higher reliability product in electrically noisy and radiated environments subject to single event upsets (SEU).
Along with the low soft error rate, the chips have a fixed hardware soft error detection (SED) circuit to detect and repair SRAM errors. This design improves prior Lattice FPGA SED implementations and has a two-layer SED for additional reliability.
All images used courtesy of Lattice Semiconductor.
