The DRAM standard includes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments, says Jedec.
Basically, the purpose of the standard is to define the minimum set of requirements for a Jedec-compliant x24 one channel SDRAM device. Note that LPDDR6 device density ranges from 4Gb to 64Gb.
LPDDR6
“JEDEC is proud to introduce LPDDR6, the culmination of years of dedicated effort by members of the JC-42.6 Subcommittee for Low Power Memories,” said Mian Quddus, Jedec’s Chairman of the Board of Directors.
“By delivering a balance of power efficiency, robust security options and high performance, LPDDR6 is an ideal choice for next-generation mobile devices, AI and related applications to thrive in a power-conscious, high-performance world.”
High performance
The performance aspect addresses the needs of AI applications, explains JEDEC. LPDDR6 employs a dual sub-channel architecture that allows for flexible operation while maintaining a small access granularity of 32 bytes.
Other performance features include 2 sub-channels per die and 12 data signal lines (DQs) per sub-channel to help optimise channel performance
Each sub-channel also includes four command/address (CA) signals, optimised to reduce ball count and improve data access speed, says Jedec.
Efficiency
In terms of power efficiency, the standards body will again have one eye on the demands of AI. Features of LPDDR6 include operating with a lower voltage and low power consumption capable VDD2 supply as compared to LPDDR5.
Additional power-saving features include alternating clock command inputs being used to enhance performance and efficiency. There is also Dynamic Voltage Frequency Scaling for Low power (DVFSL), which lowers the VDD2 supply during low-frequency operation to reduce power consumption.
Finally, a Dynamic Efficiency mode uses a single sub-channel interface for low-power, low-bandwidth use cases.
Security
Thirdly, there is the security aspect.
LPDDR6 includes Per Row Activation Counting (PRAC) to support DRAM data integrity. And Carve-out Meta mode is defined to improve system reliability, by allocating specific memory regions for critical tasks.
There is also support for programmable link protection schemes and on-die error correction code (ECC).
Finally, it is capable of supporting Command/Address (CA) parity, error scrubbing, and memory built-in self-test (MBIST) for enhanced error detection and system reliability.
Organisations
Organisations involved in the development of the standard include Advantest Corporation, Cadence, Keysight Technologies, MediaTek, Qualcomm, Samsung, SK Hynix, and Synopsys.
“The requirements for AI inference continue to grow as AI models mature and are deployed throughout the network edge and in multiple endpoint devices,” said Boyd Phelps, General Manager of the Silicon Solutions Group at Cadence.
“These edge devices demand high-performance processing and greater memory bandwidth while maintaining cost, power efficiency and reliability. LPDDR6 memory is an ideal solution, providing the speed, bandwidth and capacity needed to efficiently implement AI inference.”
To download JESD209-6, visit the JEDEC website.
Image: Samsung – Edge AI
