Previously, we examined the basic structure and combinational logic of a parallel-load shift register that I created in LTspice. Figure 1 conveys the structure and interconnection of the register’s memory units.
Figure 1. Two flip-flops and their associated logic gates in an LTspice parallel-load shift register.
In this article, we’ll observe the operation of this register and explore some of its design details.
Using Jumpers to Create Digital Data
As you may recall from the previous article, this register is a four-bit device. Each of the schematic’s four bits has an input signal named BITn, where n is a whole number in the range of 0 to 3. Figure 2 shows my solution to the problem of how to conveniently specify the preselected four-bit digital word for parallel-load operations.
Figure 2. Parallel-load values are assigned with the help of LTspice jumper components.
The components labeled X1, 2, 3, 4, and 5 are jumpers. The purpose of the jumper component, which can be found in LTspice’s “Misc” library, is mostly visual. The jumper symbol conveys the same idea as a physical jumper on a circuit board—it allows two nets with different names to be electrically connected.
As well as the four BIT signals, there’s also the RELOAD signal. As shown in Figure 3, RELOAD is the primary input of the first flip-flop in the shifting sequence. This means that RELOAD holds the bit that shifts into the register as other bits are shifting out.
Figure 3. As register data is shifted out, new data is shifted in via the RELOAD signal.
Referring back to Figure 2, you’ll see that I’ve tied RELOAD to ZERO. This means that the register will be empty—filled with zeros—once it has shifted out all of its bits. If you want the register to repeatedly shift out the preselected sequence, you can connect RELOAD to the output of the final flip-flop.
Demonstration of a Parallel Load
Figure 4 shows how the register’s two control signals, PARALLEL-LOAD and SHIFT-CLK, are generated. Because I specified a period of 1 ms with the PULSE function, the register has a shifting frequency of 1 kHz.
Figure 4. Generating the register’s control signals. The shifting frequency is 1 kHz.
As Figure 5 shows, the PARALLEL-LOAD signal is active high for the first low-to-high transition of the shift clock. Parallel data is thus loaded into the register during the system’s first clock cycle.
Figure 5. The output transitions show the relationship between the shift clock and the active-high PARALLEL-LOAD signal.
For each clock cycle after that, the rising edge of the clock coincides with a new serial bit appearing on the output of the final flip-flop, which is also the output of the shift register.
We can more easily visualize the shifting action if we examine the signal activity in Figure 6. The red trace represents the output of the first flip-flop in the sequence.
Figure 6. The output of the first flip-flop in the shift sequence when it’s first parallel-loaded with logic-high, then reloaded with logic-low.
Notice how both transitions of FIRST-FF-OUT coincide with the rising edge of the shift clock. The signal goes to logic-high at the first transition because BIT3 is tied to ONE. It then goes to logic-low at the second transition because the RELOAD signal is tied to ZERO.
Shifting Data Through the Register
Next, let’s take a look at what happens after the parallel load operation. For this simulation, I’m using the jumper settings shown in Figure 7. Instead of 0101, our four-bit word is now 0001.
Figure 7. Jumper settings for the new simulation.
First, BIT3 is loaded with the logic-high value. Figure 8 shows how that logic-high signal then propagates through the shift register—from BIT3 to BIT2 to BIT1, and finally to BIT0.
Figure 8. A timing diagram for all four flip-flops in the register.
You can identify the serial bit stream by observing SERIAL-OUT at integer multiples of 1 ms. The outputs of the flip-flops transition at the clock’s rising edge; we therefore want to sample on the falling edges, when the output signals are stable.
For example, the first three rising edges in the above timing diagram align with 0.5 ms, 1.5 ms, and 2.5 ms. The proper sampling instants are therefore 1 ms, 2 ms, and 3 ms. This is demonstrated by the dotted white lines in Figure 9.
Figure 9. The preselected four-bit word (0001) appears in serial format on the output of the last flip-flop (SERIAL-OUT).
Propagation Delay and Simulation Timestep
As we discussed earlier in this article series, accurately simulating digital circuits in LTspice sometimes requires us to specify custom device parameters. In this case, you’ll need to specify a propagation delay and a maximum timestep to ensure that your shift register works reliably.
LTspice’s default propagation delay (Td) is zero, meaning that signals propagate instantaneously from input to output. Without any delay, the output signal from one flip-flop can change states so quickly that the next flip-flop in the sequence doesn’t have time to sample the signal in response to the clock’s rising edge.
The result is that bits don’t propagate through the register. You can avoid this problem by specifying a reasonable Td value for each flip-flop. I used 1 μs, as you can see in Figure 10.
Figure 10. The time delay specification for the shift register.
Ringing on the flip-flop output signals is another strange problem that you may encounter. This is pictured in Figure 11.
Figure 11. An example of ringing following flip-flop output transitions.
The close-up view in Figure 12 lets us see the oscillations more clearly.
Figure 12. A close-up of the spurious oscillations in Figure 11.
The ringing results from some sort of conflict between the LTspice simulation engine and the way in which digital components generate timestep information. I managed to eliminate the problem by specifying an appropriate maximum timestep for the simulation. As shown in Figure 13, I chose a maximum timestep of 50 ns, which is shorter than the 100 ns rise/fall time I selected for the flip-flops (Figure 10).
Figure 13. Specifying the maximum simulation timestep.
Wrapping Up
In a future article, I’ll demonstrate the use of this shift register as part of a mixed-signal modulation system. Until then, I hope that this LTspice project helps you to more effectively incorporate digital circuitry into your simulations.
All images used courtesy of Robert Keim
