One of the fundamental challenges in the history of computing has been the mismatch between compute speed and memory access. On a computer architecture level, this challenge has led to the advent of faster memories and concepts like caching to help mitigate these challenges.
The challenge in the Internet of Things (IoT) devices is apparent, as mismatches between clock frequencies and non-volatile memory access read frequencies bottlenecks functions like over-the-air (OTA) updates and general computing.
An example of a memory bottleneck. Image used courtesy of Intel
To address this, companies are looking toward new forms of non-volatile memory as the solution, with STT-MRAM being a promising candidate.
This week, Renesas announced a new circuit technology to enable high-speed STT-MRAM on the 22 nm process. This article will look at magnetoresistive random access (MRAM), STT-MRAM, and Renesas’ latest announcement.
Basics Behind MRAM
Regarding non-volatile memory technology, many are hailing MRAM as the next big thing.
The technology leverages the relationship between a magnetic material’s relative polarity and resistance. In essence, their resistance changes when two magnets are placed near one another, depending on the location of their poles relative to one another.
For example, if one magnet’s north pole is aligned with the other’s south pole, the junction’s resistance will be low, and vice versa.
MRAM cells at both Logic 1 and 0 states. Screenshot used courtesy of Microchip
MRAM exploits this change in resistance, as manipulated by a magnet’s polarity, as a state where the device can use it to store bits in memory. A current can influence the polarity of each magnet in a given direction, and a differential sense amplifier can then read out the resulting state.
This type of memory offers several key advantages over other forms of non-volatile memory, such as high memory density and low active read/write currents.
What is STT-MRAM?
Within the world of MRAM, many different technologies exist. Of these, one of the more promising technologies is STT-MRAM.
STT-MRAM is a variation of MRAM in which the spin of nearby electrons can influence the polarity of magnetic tunnel junction (MTJ). In this form of MRAM, the electron spin is manipulated by a polarizing current that passes through a thin magnetic layer, transferring the angular momentum into this layer and hence changing the electron spin.
An STT-MRAM cell. Image used courtesy of Avalanche Technology
Compared to other forms of MRAM, STT-MRAM has the benefits of even lower power and the ability to scale even further. According to many, STT-MRAM has the potential to become a leading storage technology as it offers performance comparable to DRAM and SRAM but can scale below 10 nm, which can challenge the cost of flash.
Faster Read/Write Operations at 22 nm
This week, Renesas made headlines when it announced that it had developed a new circuit technology that allows faster read/write operations in STT-MRAM at the 22 nm node.
The major innovation reported by Renesas was a way to resolve challenges relating to MRAM’s low different sense voltages leading to slow read/write and poor reliability, especially at high temperatures.
To resolve this issue, Renesas proposed a new technology that utilizes capacitive coupling to boost the voltage at the input of the differential amplifier. The result is that STT-MRAM states can be read quicker and more reliably, even when currents are low.
The floor layout of Reneas’s test chip. Image used courtesy of Renesas
Using this technique, Renesas claims to have achieved a 30% decrease in mode transition time for the write operation, which improves the speed of the write operation overall.
Engineers verified this on a test chip built on a 22nm process, including a 32 Mbit embedded MRAM memory cell array. The test chip was reported to achieve a 5.9 ns random read access time and a write throughput of 8.8 MB/s at a maximum temperature of 150°C.
Interested in other memory technologies? Read on in the articles down below.