According to Bellezza’s patent application for the processes, features include:
’(1) Low-Temperature Fusion: Operates below 400 °C, and even as low as 200 °C-well within the CMOS thermal budgets. The process uses pressure of 50-100 PSI 10 and low temperature heat to create the fused interconnects.
(2) Substrate Engineering: Uses iron iron/nickel plating treated to form Martensite crystals, which absorb carbon graphene during heating. This creates a true alloy-like fusion.
(3) Solderless Integration: Avoids traditional soldering, solving the issue of graphene’s poor bonding with metals.
(4) Ultra-Low Resistance: The electrical resistance of the interconnects is nearly undetectable, boosting speed and thermal efficiency of the circuit.
(5) Environmental Edge: Aims to replace copper with graphene, which is safer and more environmentally friendly and sustainable.
The fusion-based process according to embodiments of the present invention can be longer lasting compared to conventional interconnects for several reasons, such as, for example,
(1) Metallurgical Bonding: The graphene is fused into a martensitic alloy substrate (iron/nickel), creating a true atomic-level bond. This is more like an alloy than a surface coating, which means it’s less prone to delamination, oxidation, or electromigration.
(2) No Solder, No Adhesives:Eliminates weak interfaces that typically degrade over time.
(3) Thermal Stability: Martensite structures are known for high hardness and resistance to thermal cycling, which could make the interconnects more resilient under fluctuating chip temperatures.
(4) Graphene Fusion Absorption: The graphene isn’t just layered-it’s absorbed into the substrate, which may reduce degradation from environmental exposure or mechanical stress.
A further aspect of the present invention provides for a 2D direct graphene deposition process using chemical synthesis.
This process includes
(1) Surface-Level Integration: Graphene is deposited on top of the CMOS substrate, which can be more vulnerable, as compared to the fusion process, to delamination or interface breakdown over time.
(2) Doping Stability: Intercalation doping improves conductivity, but dopants can diffuse or degrade under heat and electrical stress, potentially reducing performance over time.
(3) Standard substrate: While CMOS-compatible, it lacks the metallurgical robustness of fused martensitic alloy approach.
If it is a priority for maximum durability and minimal degradation over decades of operation, the fusion-based method has the edge. It’s more like building graphene into the bones of the chip, rather than painting it on the surface.
The 2D Direct Graphene Deposition Process may prove useful, for example, in consumer products, but admittedly, it is not as long lasting as the fusion process. Given the frequency of upgrades to consumer computers, it may work just fine for such devices.’
A full description of the processes can be found in Belleza’s patent application for them at:
https://thermoelectric-graphene.com/wp-content/uploads/2025/09/APB1PAU07_drawings.pdf
