Annealing processors are designed specifically for addressing combinatorial optimisation problems, where the task is to find the best solution from a finite set of possibilities.
With CMOS ICs it is necessary for the components of annealing processors to be fully “coupled.” However, the complexity of this coupling directly affects the scalability of the processors.
Led by Professor Takayuki Kawahara, researchers from the Tokyo University of Science, have developed and successfully tested a scalable, fully coupled annealing processor incorporating 4096 spins on a single board with 36 CMOS chips.
According to Prof. Kawahara, “We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing preprocessing at the edge for the cloud. Using the unique processing architecture announced by the Tokyo University of Science in 2020, we have realized a fully coupled LSI on one chip using 28nm CMOS technology. Furthermore, we devised a scalable method with parallel-operating chips, and demonstrated its feasibility using FPGAs in 2022.”
The processor incorporates two distinct technologies developed at the Tokyo University of Science. This includes a “spin thread method” that enables 8 parallel solution searches, coupled with a technique that reduces chip requirements by about half compared to conventional methods. Its power needs are also modest, operating at 10MHz with a power consumption of 2.9W (1.3W for the core part). This was practically confirmed using a vertex cover problem with 4096 vertices.
In terms of power performance ratio, the processor outperformed simulating a fully coupled Ising system on a PC (i7, 3.6GHz) using annealing emulation by 2,306 times. Additionally, it surpassed the core CPU and arithmetic chip by 2,186 times.
The successful machine verification of this processor suggests the possibility of enhanced capacity.
4096 spins
“In the future, we will develop this technology for a joint research effort targeting an LSI system with the computing power of a 2050-level quantum computer for solving combinatorial optimization problems,” says Kawahara, “the goal is to achieve this without the need for air conditioning, large equipment, or cloud infrastructure, using current semiconductor processes. Specifically, we would like to achieve 2M (million) spins by 2030 and explore the creation of new digital industries using this.”
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