For 5nm and better nodes where yield ramp heavily relies on chain diagnosis, the tool can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles.
“Tessent Hi-Res Chain represents a major leap forward in our ability to rapidly identify and address
yield-limiting factors in advanced IC designs,” says Siemens vp Ankur Gupta.
By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), Tessent Hi-Res Chain transforms failing test cycles into actionable insights.
The solution employs layout-aware and cell-aware technology to pinpoint a defect’s most probable failure mechanism, logic location, and physical location.
Tessent Hi-Res Chain claims to offer precise defect isolation, even for point defects deep withi control signal networks, while maintaining the Tessent accuracy rate, with over 80 percent of its generated reports consistently confirmed through FA processes using Tessent technology.
For more: www.siemens.com/tessent.
