As we know from earlier articles, the switching frequency of a practical Class D amplifier doesn’t always match its resonant frequency. This mismatch can result either from component non-idealities or the intentional operation of the amplifier at a slightly different frequency. In both cases, the mistuned LC circuit produces a reactive load.
In this article, we’ll examine how the performance of a Class D amplifier is affected when its load network has a reactive component. We’ll also explore the impact of parasitic capacitances at the input of the tuned circuit. The discussion of each non-ideality will conclude with an example problem.
Power Loss Due to Reactive Loads
Figure 1 shows the complementary voltage-switching Class D amplifier that we’ve been exploring over the past few articles.
Figure 1. Complementary voltage-switching Class D configuration.
For the above amplifier, the ideal inductance value is Ls. The ideal capacitance is Cs. Together, Ls and Cs give us an ideal resonant circuit tuned to the switching frequency.
However, suppose that the inductance is actually (Ls + La) because of component non-idealities. As illustrated in Figure 2, we now have an additional inductance in series with the ideal tuned circuit.
Figure 2. A Class D amplifier with a mistuned LC circuit due to component non-idealities.
The ideal tuned circuit in the orange box acts as a short at the switching frequency. The remaining load network comprises the series connection of La and RL. Since the load is inductive, we see in Figure 3 that the output current (iRF) lags behind the fundamental component of the square wave at node A (VA).
Figure 3. Above the resonant frequency, the current lags the fundamental component of the square wave voltage.
From our first discussion of Class D operation, we know that an ideal Class D amplifier has a theoretical 100% efficiency and an output power of PL = 2VCC2/π2RL. Let’s see how the phase difference in Figure 3 influences these parameters.
The Effect of a Reactive Load on Output Power
We need to know the load current’s peak value (Ip) to calculate the power delivered to the load. The load current is produced by the fundamental component of VA. Using the Fourier series representation to express VA in terms of its constituent frequency components, we get:
$$V_A~=~frac{V_{CC}}{2} ~+~frac{2V_{CC}}{pi}~sum_{n=1}^{infty}~frac{sin((2n~-~1)omega_{0}t)}{2n~-~1}$$
Equation 1.
where ⍵0 is the angular fundamental frequency of the square wave.
From Equation 1, we see that the fundamental component of VA has a peak value of 2VCC/π. Both the equation and its result are unchanged from when we discussed the ideal Class D amplifier.
The same can’t be said of Equation 2. The load impedance (ZL) at the switching frequency (⍵0) is no longer simply equal to RL. Instead, it consists of the series connection of La and RL, giving us an impedance of:
$$Z_L ~=~ R_L ~+~ j L_a omega_0 ~=~ R_L ~+~ j X_L$$
Equation 2.
where XL is the inductive reactance. Using Ohm’s law, the current flowing through the load is:
$$i_{RF} ~=~ frac{V_{A, ;fundamental}}{Z_L} ~Rightarrow~ i_{RF}(t) ~=~ frac{2 V_{CC}}{pi |Z_L|} sin Big (omega_0 t ~-~ arctan(frac{X_L}{R_L}) Big )$$
Equation 3.
From Equation 3, the peak value of iRF is (I_p ~=~frac{2V_{CC}}{pi |Z_L|}). Recalling that irms is equal to Ip/(sqrt{2}), we can now calculate the average power delivered to the load:
$$P_{L} ~=~ R_L i_{rms}^2 ~=~ frac{2V_{CC}^2}{pi^2 |Z_L|^2}~times~ R_L$$
Equation 4.
This equation can be rewritten as:
$$P_{L} ~=~ Big ( frac{2V_{CC}^2}{pi^2 R_L }Big ) ~times~ rho^2$$
Equation 5.
where:
(frac{2V_{CC}^2}{pi^2 R_L}) is the power that would be delivered to a purely resistive (XL = 0) load
⍴ = RL/|ZL|
Since the load impedance includes a reactive component, ⍴ is less than unity. The product of Equation 5 is therefore less than the ideal load power.
It’s not surprising that adding a reactive component reduces the load power—it’s easy to see from Equation 2 that a reactive term increases the magnitude of the load impedance (|ZL|), which reduces the output current.
The Effect of a Reactive Load on Efficiency
In the previous section, we calculated the output power. To find the efficiency, we also need to determine the input power provided by the supply. The input power is equal to the supply voltage multiplied by the average value of the current drawn from the supply.
In Figure 3’s waveforms, the current is drawn from the supply during the first half-cycle of the switching period (from t = 0 to t = T/2), which is when the upper switch is ON. In the second half-cycle, the upper switch is open and no current can be drawn from the supply. During this half of the cycle, the energy stored in the LC circuit circulates through the load and the lower switch. Therefore, the DC component of the supply current is:
$$begin{eqnarray}I_{dc} ~&=& ~frac{1}{T} int_{0}^{T/2} i_{RF}(t) dt \&=& ~frac{1}{T} int_{0}^{T/2} frac{2 V_{CC}}{pi |Z_L|} sin Big (omega_0 t ~-~ arctan(frac{X_L}{R_L}) Big ) dtend{eqnarray}$$
Equation 6.
Note that the integral is taken over the time interval when the upper switch is ON.
The seemingly intimidating equation above simplifies to:
$$I_{dc} ~=~ frac{2V_{CC}}{pi^2 |Z_L|^2}~times~ R_L$$
Equation 7.
Multiplying Equation 7 by VCC, we find the input power:
$$P_{CC} ~=~ frac{2V_{CC}^2}{pi^2 |Z_L|^2}~times~ R_L$$
Equation 8.
This is equal to the output power (Equation 4), resulting in an ideal efficiency of 100%. Even though a reactive load reduces the output power, it doesn’t degrade the amplifier’s efficiency.
Example: Power Reduction Caused by a Reactive Load
When discussing the ideal Class D amplifier, we designed a complementary voltage-switching Class D amplifier to deliver 20 W to a purely resistive 50 Ω load. We saw that this requires a supply voltage of VCC = 70.2 V and transistors that can safely conduct a maximum current of 0.89 A. You can verify these numbers by substituting RL = 50 Ω and XL = 0 into Equations 3 and 5 of this article, as the purely resistive load is a special case of the analysis we provided above.
This time, let’s assume that a reactance of 50 Ω appears in series with RL = 50 Ω. What would the output power and maximum collector current be?
First, let’s find ⍴. With RL = 50 Ω and XL = 50 Ω, we have:
$$rho ~=~ frac{R_L}{|Z_L|} ~=~ frac{50}{sqrt{50^2 ~+~ 50^2}} ~=~frac{1}{sqrt{2}}$$
Equation 9.
Plugging this value of ⍴ into Equation 5, we observe that the output power is halved because of the reactive component of the load network. The output power with a resistive load was 20 W, so the new output power is 0.5 × 20 = 10 W.
In Equation 3, we saw that the maximum current is (I_p~=~frac{2V_{CC}}{pi |Z_L|}). |ZL| is equal to RL/⍴, and VCC is given as 70.2 V at the start of the example. We therefore have a peak current of:
$$I_p~=~frac{2V_{CC}}{pi |Z_L|}~=~frac{2~times~70.2}{pi~times~50~times~sqrt{2}}~=~0.63~text{A}$$
Equation 10.
The maximum current passing through the transistor reduces from 0.89 A (in the ideal amplifier) to 0.63 A. As stated above, the output power halves from 20 W to 10 W.
Power Loss Due to Parasitic Capacitances
Figure 4 shows another important non-ideality of Class D amplifiers: parasitic capacitances.
Figure 4. Cc1 and Cc2 model the parasitic capacitances that exist between node A and the supply rails.
In the above figure, Cc1 and Cc2 are the equivalent parasitic capacitances that appear in parallel with Q1 and Q2. When the square wave transitions between the supply rails, the capacitances cause power loss at node A. Let’s see how this affects the amplifier’s performance.
Figure 5(a) provides a simplified model of the circuit during the first half-cycle of operation. Figure 5(b) does the same for the second half-cycle. The voltages at Cc1 and Cc2 for each half-cycle are indicated in green.
Figure 5. Voltages at Cc1 and Cc2 when node A is driven to VCC (a) and ground (b).
In the first half of the cycle, the upper switch (S1) is closed and the lower switch (S2) is open. The square wave at node A is therefore driven to VCC. Because both of its terminals are at the same potential, Cc1 has no charge. Meanwhile, Cc2 is charged to VCC.
At the beginning of the second half-cycle, S2 closes and S1 opens. The voltage at node A is driven—ideally instantly—to ground. When this transition occurs, S2 charges Cc1 to VCC and discharges Cc2 from VCC to 0 V. The energy that was initially stored in Cc2 is therefore lost.
Using the formula for energy storage in a capacitor, we can calculate the initial energy of Cc2:
$$U_1 ~=~ frac{1}{2} C_{c2} V_{CC}^2$$
Equation 11.
This energy is dissipated as heat in S2 when it closes. At the same time, Cc1 is charged to VCC. Denoting the energy that gets stored in Cc1 as U2, we have:
$$U_2 ~=~ frac{1}{2} C_{c1} V_{CC}^2$$
Equation 12.
To understand how this affects power loss, we need to review the behavior of the simple RC circuit in Figure 6.
Figure 6. An RC circuit to charge a capacitor.
When we close the switch in this circuit, the voltage source supplies the energy to charge the capacitor. However, it can be shown that only half of the energy supplied by the battery is stored in the capacitor. The other half is dissipated as heat in the resistor.
Interestingly, the energy dissipated in the resistor is independent of the resistance value. In the Class D amplifier, this means that an amount of energy equal to U2 is dissipated in the switch-on resistance when S2 closes and charges Cc1. Therefore, the total energy dissipated in S2 is U1 + U2.
A similar sequence of events happens at the beginning of the next half-cycle, when node A is driven back to VCC. At this instant, the switch S1 closes to discharge Cc1 to 0 V and charge Cc2 to VCC. This leads to another energy loss of U1 + U2. Therefore, the total energy lost due to the parasitic capacitances over a full cycle is:
$$U_{total} ~=~ 2(U_1 + U_2) ~=~ (C_{c1}~+~C_{c2}) V_{CC}^2$$
Equation 13.
Since this amount of energy is lost in every RF cycle, the power dissipated is:
$$P_{dissipated} ~=~ (C_{c1}~+~C_{c2}) V_{CC}^2 f$$
Equation 14.
where f is the switching frequency.
Because this power is dissipated in the switches, there’s no effect on the amplifier’s output power—only on its efficiency.
Example: Efficiency Reduction Caused by Parasitic Capacitances
A complementary voltage-switching Class D amplifier powered by VCC = 70.2 V delivers 20 W to a 50 Ω load. However, two 20 pF parasitic capacitances (Cc1 = Cc2 = 20 pF) exist at the input of its tuned circuit. If the switching frequency is 10 MHz, how much power is lost due to the parasitic capacitors? What is the efficiency of the amplifier?
Plugging the numbers into Equation 14, we obtain:
$$begin{eqnarray}P_{dissipated}~ &=& ~(C_{c1}~+~C_{c2}) V_{CC}^2 f \&=& ~(20 ~+~ 20) ~times~ 10^{-12} ~times~ 70.2^2 ~times~ 10 ~times~ 10^6 \&=& ~1.97 ~text{W} end{eqnarray}$$
Equation 15.
The capacitances cause 1.97 W of power loss.
As we saw above, power losses due to parasitic capacitances don’t affect the output power. They only increase the power provided by the supply. Therefore, efficiency can be calculated as:
$$eta ~=~ frac{P_{out, ideal}}{P_{out, ideal}~+~P_{dissipated}} ~=~ frac{20}{20~+~1.97}~=~91%$$
Equation 16.
Because of the parasitic capacitances, the Class D amplifier has an efficiency of 91%, whereas the idealized Class D amplifier had a theoretical efficiency of 100%.
Wrapping Up
In this article, we learned about two non-idealities—reactive load components and parasitic capacitances—that affect Class D amplifiers. We saw that a reactive load reduces the amplifier’s output power but not its efficiency; the parasitic capacitances, on the other hand, reduce efficiency but not output power.
As in the preceding articles about the Class D amplifier, our discussion was based on the complementary voltage-switching configuration. In the next article, we’ll introduce a different configuration: the transformer-coupled voltage-switching Class D amplifier.
All images used courtesy of Steve Arar
